In high-density DRAMs, a great number of gate electrodes (i.e. word lines) are very closely spaced one another in a memory cell and the gap between the word lines is very narrow. Connection, for example, between the bit line and the source and drain, is made through such an extremely cramped gap. As the density of DRAMs increases, such a gap is made smaller and smaller. Existing photolithography techniques, however, present such a problem that the size of openable contact holes cannot be reduced with the demagification ratio of the word line pitch, thereby giving rise to the overlapping of a hole pattern with a word line.
Therefore, the formation of contact to the source and rain must be carried out in a self-alignment manner with respect to the word line. Self-alignment up to the generation of 64M-bit DRAMs has been done using a spacer, made of an insulating layer, formed on the side wall of a gate.
Originally, such a spacer is used to hold a source region (or a drain region) being formed and a gate electrode at a given distance from each other when carrying out an implantation of impurities, particularly in transistors in a peripheral circuit (for example, ones in row and column decoders). In other words, an extraction electrode, made of polycrystalline silicon, is formed in a self-align manner with the help of a spacer, and connection to upper-layer wirings is established through the extraction electrode.
Referring now to the drawings, the above-described prior art technique is described. FIGS. 5a-5f are cross-sectional views depicting successive stages of the fabrication of a DRAM by means of a conventional self-alignment technique. Each of FIGS. 5a-5f depicts in cross section a memory cell on the left side and a peripheral transistor on the right side.
First, as shown in FIG. 5a, an isolation region 2 and a gate oxide 3 are formed on a silicon substrate 1. Material from which a gate electrode is made is deposited, and material from which an insulating layer is made is deposited. These two deposited layers are etched one after another using the same mask, whereby a gate electrode 4 constituting a word line and an upper insulating layer 5 are formed. Further, using the gate electrode 4, upper dielectric layer 5, and isolation region 2 as a part of a mask, an implantation of ions is carried out from above the silicon substrate 1 to create a lightly doped source (drain) 6. Usually, peripheral transistors are formed by CMOSs, in which case their type (p. n) is decided as required and they are formed using a resist mask or the like.
Next, as shown in FIG. 5b, a first insulating layer 7 having an adequate thickness is deposited. Then, as shown in FIG. 5c, the entire surface of the first insulating layer 7 is anisotropically etched in such a way that the first insulating layer 7 is left only on the side walls of the gate electrode 4. As shown in FIG. 5c-L(eft), by using such a residual first insulating layer 7 as a part of a mask, an implantation of ions, as indicated by arrows 20, is carried out to create a heavily doped source (drain) 16. In other words, the residual first insulating layer 7 serves as a spacer determining a transistor offset length df. Here, the heavily doped source (drain) 16 is defined as a region with a dosage of lE20cm-3 ions or more, and the offset length df is the distance from the gate end to the region 16. The reliability of transistors and the short channel effect are influenced by the offset length df. In order to provide favorable transistor characteristics, the spacer is required to have a thickness of 120 nm or more even in a heat treatment in which heat treatment time is shortened to a production limit.
If, during the foregoing ion implantation, impurities enter a memory cell when carrying out the aforesaid ion implantation 20, this is likely to damage that memory cell. Therefore, as shown in FIG. 5c-R(ight), the memory cell is masked with a resist 15. More specifically, such masking is done by giving a resist mask used to form n-type peripheral transistors a particular mask pattern so as to cover the memory cell. Now, the transistor fabrication is completed.
Next, an extraction electrode 13, made of polycrystalline silicon, is formed as follows. As shown in FIG. 5d-L, a second insulating layer 14 which is a comparatively thin layer is deposited on the entire surface of the silicon substrate 1, and a self-aligned contact 9 is pattern-formed using a photoresist 8. For the case of 64M-bit DRAMs, the gap between word lines is below 0.5 .mu.m, and resist hole patterns have a limitation of 0.4 .mu.m. Additionally, taking into account the fact that the generation of 64M-bit DRAMs has an alignment accuracy limitation of 0.1 .mu.m, the occurrence of the overlap of the contact 9 and the gate electrode 4 is unavoidable. Therefore, in order to open up a contact in a self-align manner, contact etching must be carried out for a distance corresponding to the film thickness of the second insulating layer 14, that is, as deep as the second insulating layer 14 is thick. The second insulating layer 14 is given a comparatively thin film thickness and thus the gap between gates is not filled up with the layer 14. Therefore, the surface of the silicon substrate can be exposed by carrying out a slight etching, whereby a contact can be opened in a self-align manner. If such an etching extends beneath the second insulating layer 14, this leads to an unwanted contact to a word line since a resist opening overlaps with the gate electrode 4. Self-alignment becomes unavailable as a result.
Next, as shown in FIG. 5e, a polycrystalline silicon layer 10 is deposited. Then, the polycrystalline silicon layer 10 is subjected to an implantation of ions as indicated by arrows 11. Further, as shown in FIG. 5f, by using a resist mask 12, the polycrystalline silicon layer 10 is processed into a predetermined form to form the extraction electrode 13. The polycrystalline silicon of the polycrystalline silicon layer 10 is easily etched at high etch selectivity with respect to the underlaying insulating layers 7 and 14 by a reactive ion etching technique (RIE) sing, for example, HBr. Therefore, no residual matters will be left at steep step portions created by the gate electrode 4 and thus a residue-free process can be obtained.
The extraction electrode 13 is pre-formed for ease of connection. More specifically, when threading down between closely arranged word lines so as to establish connection, what is required is just to open a contact as far as the extraction electrode 13. Therefore, self-alignment with respect to a word line is possible. If the extraction electrode 13 is made of such upper-layer wiring materials as aluminum and metal silicide, over etching cannot be carried out due to low etch selectivity with respect to the first and second insulating layers 7 and 14 and therefore the residue is left at steep step portions created by the gate electrode 4. In order to avoid such a problem, the extraction electrode 13 is preferably made of polycrystalline silicon.
The above-described fabrication technique, however, is not suitable for the next generation, 256M-bit DRAMs.
When trying to increase the DRAM density, it is desirable that the dimensions and the film thickness should be reduced at the same demagnification ratio. If such is possible, the foregoing fabrication technique of FIGS. 5a-5f becomes practical. However, it is not possible to reduce the spacer thickness specifying the offset length df with the demagnification ratio of the word line pitch. Under actual heat treatment conditions, it is very difficult to reduce the diffusion of impurities used to create heavily doped regions at the same demagnification ratio. Therefore, if the spacer thickness is reduced too thin, the short channel effect becomes significant resulting in the malfunction of transistors. As a result, the spacer-thickness demagnification ratio must be lower than the word-line demagnification ratio.
FIGS. 6a to 6e illustrate in cross section successive stages of the fabrication of a high-density DRAM in which an extraction electrode is formed in the same way as shown in FIGS. 5a-5f, but under a different condition where the word line pitch is further made smaller.
In FIG. 6a, the lightly doped source (drain) 6 is created. In the 256M-bit DRAM class, a word line-to-word line gap dw is somewhere between 0.20 .mu.m and 0.25 .mu.m, while the required spacer thickness is from 0.125 .mu.m to 0.150 .mu.m. he first insulating layer 7 is deposited (see FIG. 6b). hen, the first insulating layer 7 is so etched back that its residue is left on the side walls of the gate electrode
As shown in FIG. 6c, a gap between each word line (i.e. each gate electrode 4) is filled up with the first insulating layer 7. If self-alignment is tried under such state in the same way as shown in FIGS. Sd to Sf, the silicon surface of the silicon substrate 1 will not be exposed by an etching carried out to the second insulating layer 14 alone (see FIG. 6d).
If anisotropic etching is carried out until the silicon surface has emerged between the gate electrodes 4, this results in removing parts of the insulating layers 7 and 14 from the side walls of the gate electrode 4 (see PT1 of FIG. 6e). If an extraction electrode is formed between the gate electrodes 4 whose side wall insulating layers have been removed partly, both the electrodes come to contact with each other. For the case of the 64M-bit DRAM class, there is no need for worrying about such a problem because dw is from 0.4 .mu.m to 0.5 .mu.m and df is about 0.15 .mu.m. For the case of the 256M-bit DRAM class, however. there are difficulties in forming extraction electrodes since dw is reduced while the spacer thickness remains unchanged.
It is understood from the above that, when making highdensity DRAMs by means of the above-described fabrication technique, the spacer thickness conflicts with the in-cell self-alignment.